The present invention relates to electronic circuits, and particularly relates to a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any leakage.
In older generations of CMOS technologies, the standard value of the supply voltage powering the chip was 5 volts, +/xe2x88x9210%. Under that setting, the standard design of the P-driver of the Input/Output (hereinafter I/O) involved coupling the N-well of the P-driver to VDD permanently in order to permanently ensure that the N-well potential was always higher than any other voltages in the circuit. This design prevented any unwanted DC leakage through the P-driver.
In conventional CMOS integrated circuits, large N-wells are formed on p-type substrates, and PMOS transistors are formed in these N-wells. Typically, all of the P-channel transistors of the P-driver are formed in a common N-well and have substrate or terminals that are electrically integral with or connected to the N-well.
In sub-micron CMOS technologies, VDD supply voltages had to scale down with the sub-micron CMOS technologies. A VDD supply voltage of 3.3 volts became standard for I/O power. This created the problem of interfacing 3.3 volt I/Os to 5 volt supplied I/Os. The problem materialized when the P-driver was tri-stated.
The P-driver is tri-stated when it is in a xe2x80x9ctri-statexe2x80x9d or xe2x80x9chigh impedancexe2x80x9d mode. Tristate mode occurs when the low voltage CMOS core logic circuitry associated with the tristate P-driver is not driving a bus connected to the P-driver. Instead, the low-voltage CMOS core logic circuitry is either (1) receiving data from the bus at node VPAD or (2) is not involved in any transactions occurring on the bus. In this circumstance, it is desired for the P-driver to have a high input impedance for avoiding unnecessary current sinks and for reducing overall bus inductance and capacitance.
Standard circuitry, as shown in FIG. 1, addressed this problem by doing the following:
(1) floating the N-well of the P-driver; and
(2) pulling the gate of the tri-stated P-driver to PAD voltage when the PAD voltage was 5 volts.
This standard solution worked well since the difference between 5 volts, +/xe2x88x9210%, and 3.3 volts, +/xe2x88x9210%, always exceeded Vtp, the forward conducting voltage of the P-driver, and, also equivalent to one diode drop.
In deep sub-micron CMOS technologies, VDD supply voltages continued to scale down, sometimes below the VDD supply voltages of the sub-micron CMOS technologies. VDD supply voltages of 2.5 volts and 1.8 volts became common. These low VDD supply voltages made the interface issue (the tolerance issue) between such VDD supply voltages more complicated.
The standard sub-micron circuit technique described above for having a 3.3 volt I/O tolerate a 5 volt I/O fails when the new values for the I/O VDD supply voltages and the tolerated input voltages are 2.5 volts, +/xe2x88x9210%, and 3.3 volts, +/xe2x88x9210%, respectively. This is because for a VDD of 2.75 volts (2.5 volts +10%) and a tolerated voltage of 3 volts (3.3 volts xe2x88x9210%), the voltage difference between VDD and the tolerated voltage is less than Vtp. This results in excessive and unacceptable DC leakage through the P-driver.
Therefore, a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage is needed.
The present invention provides a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage.
The voltage tolerant input/output circuit includes (1) an arbiter circuit logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P-driver is tri-stated, (2) a bias circuit logically configured to biased a floating N-well of the P-driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver is forward biased, and (3) a driver circuit comprising the P-driver.